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nand flash memory mt29f1g08aacwp, mt29f1g08aach4 mt29f1g08abchc, MT29F1G16ABCHC, mt29f1g08abch4, mt29f1g16abch4 features ? open nand flash interface (onfi) 1.0-compliant 1 ? single-level cell (slc) technology ? organization C page size x8: 2112 bytes (2048 + 64 bytes) C page size x16: 1056 words (1024 + 32 words) C block size: 64 pages (128k + 4k bytes) C device size: 1gb: 1024 blocks ? asynchronous i/o performance C t rc/ t wc: 25ns (3.3v), 35ns (1.8v) ? array performance C read page: 25s C program page: 250s (typ, 3.3v) C program page: 250s (typ, 1.8v) C erase block: 500s (typ) ? command set: onfi nand flash protocol ? advanced command set C program cache C read cache sequential C read cache random C one-time programmable (otp) mode C block lock (1.8v only) C boot block (1.8v only) C programmable drive strength C read unique id C internal data move ? operation status byte provides software method for detecting C operation completion C pass/fail condition C write-protect status ? internal data move operations supported within the device from which data is read ? ready/busy# (r/b#) signal provides a hardware method for detecting operation completion ? wp# signal: write protect entire device ? blocks 0C7 (block address 00h-07h) guaranteed to be valid with ecc when shipped from factory (3.3v only); see error management (page 83). ? blocks 0C3 (block address 00h-03h) guaranteed to be valid with ecc when shipped from factory (1.8v only); see error management (page 83). ? reset (ffh) required as first command after power- on ? alternate method of device initialization (nand_in- it) after power up 3 (contact factory) ? quality and reliability C data retention: 10 years C endurance: 100,000 program/erase cycles ? operating voltage range C v cc : 2.7C3.6v C v cc : 1.65C1.95v ? operating temperature: C commercial: 0c to +70c C extended (et): C40oc to +85oc ? package C 48-pin tsop type 1, cpl 2 C 63-ball vfbga notes: 1. the onfi 1.0 specification is available at www.onfi.org . 2. cpl = center parting line. 3. available only in 1.8v vfbga package. micron confidential and proprietary 1gb: x8, x16 nand flash memory features pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. www.datasheet.co.kr datasheet pdf - http://www..net/
part numbering information micron nand flash devices are available in different configurations and densities. verify valid part numbers by using microns part catalog search at www.micron.com . to compare features and specifications by device type, visit www.micron.com/products . contact the factory for devices not found. figure 1: marketing part number chart mt 29f 1g 08 a a c hc es :c micron technology single-supply nand flash 29f = single-supply nand flash memory density 1g = 1gb device width 08 = 8 bits 16 = 16 bits classification # of die # of ce# # of r/b# i/o a 1 1 1 common operating voltage range a = 3.3v (2.7C3.6v) b = 1.8v (1.65C1.95v) feature set c = feature set c design revision c = third revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating t emperature range blank = commercial (0c to +70c) et = extended (C40c to +85c) reserved for future use blank nand flash performance blank = standard package code wp = 48-pin tsop cpl hc = 63-ball vfbga (10.5mm x 13mm x 1.0mm) h4 = 63-ball vfbga (9mm x 11mm x 1.0mm) micron confidential and proprietary 1gb: x8, x16 nand flash memory features pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
contents general description ......................................................................................................................................... 8 signal descriptions and assignments ................................................................................................................ 8 package dimensions ...................................................................................................................................... 12 architecture ................................................................................................................................................... 15 device and array organization ....................................................................................................................... 16 asynchronous interface bus operation ........................................................................................................... 18 asynchronous enable/standby ................................................................................................................... 18 asynchronous commands .......................................................................................................................... 18 asynchronous addresses ............................................................................................................................ 20 asynchronous data input ........................................................................................................................... 21 asynchronous data output ........................................................................................................................ 22 write protect .............................................................................................................................................. 23 ready/busy# .............................................................................................................................................. 23 device initialization ....................................................................................................................................... 28 command definitions .................................................................................................................................... 29 reset operations ............................................................................................................................................ 31 reset (ffh) ............................................................................................................................................... 31 identification operations ................................................................................................................................ 32 read id (90h) ............................................................................................................................................ 32 read id parameter tables ............................................................................................................................. 33 read parameter page (ech) ...................................................................................................................... 35 parameter page data structure tables ............................................................................................................. 36 read unique id (edh) ................................................................................................................................ 38 feature operations ......................................................................................................................................... 39 set features (efh) ................................................................................................................................. 39 get features (eeh) ................................................................................................................................. 40 status operations ........................................................................................................................................... 44 read status (70h) ................................................................................................................................... 45 column address operations ........................................................................................................................... 46 random data read (05h-e0h) ................................................................................................................ 46 random data input (85h) ..................................................................................................................... 47 program for internal data input (85h) ........................................................................................... 48 read operations ............................................................................................................................................. 50 read mode (00h) ..................................................................................................................................... 51 read page (00h-30h) ................................................................................................................................ 51 read page cache sequential (31h) ..................................................................................................... 51 read page cache random (00h-31h) .................................................................................................... 53 read page cache last (3fh) .................................................................................................................. 54 program operations ....................................................................................................................................... 55 program page (80h-10h) ........................................................................................................................ 55 program page cache (80h-15h) ............................................................................................................ 56 erase operations ............................................................................................................................................ 58 erase block (60h-d0h) ............................................................................................................................ 58 internal data move operations ....................................................................................................................... 59 read for internal data move (00h-35h) ............................................................................................ 59 program for internal data move (85h-10h) ..................................................................................... 61 boot blocks .................................................................................................................................................... 62 protecting the boot blocks .......................................................................................................................... 62 block lock feature ......................................................................................................................................... 63 wp# and block lock ................................................................................................................................... 63 micron confidential and proprietary 1gb: x8, x16 nand flash memory pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
unlock (23h-24h) .................................................................................................................................... 63 lock (2ah) ................................................................................................................................................ 66 lock tight (2ch) ..................................................................................................................................... 67 block lock read status (7ah) ............................................................................................................. 68 one-time programmable operations (3.3v) .................................................................................................... 70 otp data program (a0h-10h) ................................................................................................................ 70 otp data protect (a5h-10h) .................................................................................................................. 71 otp data read (afh-30h) ........................................................................................................................ 72 one-time programmable operations (1.8v) .................................................................................................... 74 otp data program (80h-10h) ................................................................................................................. 74 random data input (85h) ..................................................................................................................... 75 otp data protect (80h-10h) .................................................................................................................. 76 otp data read (00h-30h) ........................................................................................................................ 77 write protect operation ........................................................................................................................... 80 error management ......................................................................................................................................... 83 electrical specifications .................................................................................................................................. 84 electrical specifications C ac characteristics and operating conditions ........................................................... 86 electrical specifications C dc characteristics and operating conditions .......................................................... 89 electrical specifications C program/erase characteristics ................................................................................. 91 asynchronous interface timing diagrams ....................................................................................................... 92 revision history ............................................................................................................................................ 102 rev d, production C 01/10 ......................................................................................................................... 102 rev c, production C 7/09 ............................................................................................................................ 102 rev b, production C 5/08 ............................................................................................................................ 102 rev a, production C 2/08 ............................................................................................................................ 102 micron confidential and proprietary 1gb: x8, x16 nand flash memory pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
list of tables table 1: asynchronous signal definitions ........................................................................................................ 8 table 2: array addressing (x8) ........................................................................................................................ 16 table 3: array addressing (x16) ...................................................................................................................... 17 table 4: asynchronous interface mode selection ........................................................................................... 18 table 5: command set .................................................................................................................................. 29 table 6: read id parameters for address 00h ................................................................................................ 33 table 7: read id parameters for address 20h ................................................................................................ 34 table 8: parameter page data structure ......................................................................................................... 36 table 9: feature address definitions .............................................................................................................. 39 table 10: feature addresses 01h: timing mode .............................................................................................. 41 table 11: feature addresses 80h: programmable i/o drive strength ............................................................... 42 table 12: feature addresses 81h: programmable r/b# pull-down strength ..................................................... 42 table 13: features address 90h: operation mode ........................................................................................... 43 table 14: status register definition ............................................................................................................... 44 table 15: block lock address cycle assignments ............................................................................................ 65 table 16: block lock status register bit definitions ........................................................................................ 68 table 17: error management details .............................................................................................................. 83 table 18: absolute maximum ratings ............................................................................................................ 84 table 19: recommended operating conditions ............................................................................................. 84 table 20: valid blocks .................................................................................................................................... 84 table 21: capacitance ................................................................................................................................... 85 table 22: test conditions .............................................................................................................................. 85 table 23: ac characteristics: command, data, and address input (3.3v) ......................................................... 86 table 24: ac characteristics: command, data, and address input (1.8v) ......................................................... 86 table 25: ac characteristics: normal operation (3.3v) ................................................................................... 87 table 26: ac characteristics: normal operation (1.8v) ................................................................................... 88 table 27: dc characteristics and operating conditions (3.3v) ........................................................................ 89 table 28: dc characteristics and operating conditions (1.8v) ........................................................................ 90 table 29: program/erase characteristics .................................................................................................. 91 micron confidential and proprietary 1gb: x8, x16 nand flash memory pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
list of figures figure 1: marketing part number chart .......................................................................................................... 2 figure 2: 48-pin tsop C type 1, cpl (top view) ............................................................................................... 9 figure 3: 63-ball vfbga, x8 (balls down, top view) ....................................................................................... 10 figure 4: 63-ball vfbga, x16 (balls down, top view) ...................................................................................... 11 figure 5: 48-pin tsop C type 1, cpl .............................................................................................................. 12 figure 6: 63-ball vfbga (hc) ........................................................................................................................ 13 figure 7: 63-ball vfbga (h4) 9mm x 11mm ................................................................................................... 14 figure 8: nand flash die (lun) functional block diagram ........................................................................... 15 figure 9: array organization C x8 ................................................................................................................... 16 figure 10: array organization C x16 ................................................................................................................ 17 figure 11: asynchronous command latch cycle ............................................................................................ 19 figure 12: asynchronous address latch cycle ................................................................................................ 20 figure 13: asynchronous data input cycles ................................................................................................... 21 figure 14: asynchronous data output cycles ................................................................................................. 22 figure 15: asynchronous data output cycles (edo mode) ............................................................................. 23 figure 16: read/busy# open drain ............................................................................................................. 24 figure 17: t fall and t rise (3.3v v cc ) ................................................................................................................ 25 figure 18: t fall and t rise (1.8v v cc ) ................................................................................................................ 25 figure 19: i ol vs rp (v cc = 3.3v v cc ) ............................................................................................................... 26 figure 20: i ol vs rp (1.8v v cc ) ........................................................................................................................ 26 figure 21: tc vs rp ........................................................................................................................................ 27 figure 22: r/b# power-on behavior ............................................................................................................... 28 figure 23: reset (ffh) operation ................................................................................................................. 31 figure 24: read id (90h) with 00h address operation .................................................................................... 32 figure 25: read id (90h) with 20h address operation .................................................................................... 32 figure 26: read parameter (ech) operation .............................................................................................. 35 figure 27: read unique id (edh) operation ............................................................................................... 38 figure 28: set features (efh) operation .................................................................................................... 39 figure 29: get features (eeh) operation ................................................................................................... 40 figure 30: read status (70h) operation ...................................................................................................... 45 figure 31: random data read (05h-e0h) operation .................................................................................. 46 figure 32: random data input (85h) operation ........................................................................................ 47 figure 33: program for internal data input (85h) operation .............................................................. 49 figure 34: read page (00h-30h) operation ................................................................................................... 51 figure 35: read page cache sequential (31h) operation ........................................................................ 52 figure 36: read page cache random (00h-31h) operation ....................................................................... 53 figure 37: read page cache last (3fh) operation ..................................................................................... 54 figure 38: program page (80h-10h) operaton ............................................................................................ 56 figure 39: program page cache (80h-15h) operation (start) ..................................................................... 57 figure 40: program page cache (80h-15h) operation (end) ...................................................................... 57 figure 41: erase block (60h-d0h) operation .............................................................................................. 58 figure 42: read for internal data move (00h-35h) operation ............................................................... 60 figure 43: read for internal data move (00h-35h) with random data read (05h-e0h) .................... 60 figure 44: program for internal data move (85h-10h) ....................................................................... 61 figure 45: program for internal data move (85h-10h) with random data input (85h) .................. 61 figure 46: flash array protected: invert area bit = 0 ........................................................................................ 64 figure 47: flash array protected: invert area bit = 1 ........................................................................................ 64 figure 48: unlock operation ...................................................................................................................... 65 figure 49: lock operation ............................................................................................................................ 66 figure 50: lock tight operation ................................................................................................................ 67 micron confidential and proprietary 1gb: x8, x16 nand flash memory pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 51: program/erase issued to locked block ..................................................................................... 68 figure 52: block lock read status ......................................................................................................... 68 figure 53: block lock flowchart ................................................................................................................ 69 figure 54: otp data program operation .................................................................................................. 71 figure 55: otp data protect operation .................................................................................................... 72 figure 56: otp data read operation ........................................................................................................... 73 figure 57: otp data program operation (after entering otp operation mode) ........................................... 75 figure 58: otp data program with random data input (after entering otp operation mode) ............... 76 figure 59: otp data protect operation (after entering otp protect mode) ................................................ 77 figure 60: otp data read operation ........................................................................................................... 78 figure 61: otp data read with random data read operation ................................................................ 79 figure 62: erase enable ............................................................................................................................... 80 figure 63: erase disable .............................................................................................................................. 80 figure 64: program enable ......................................................................................................................... 81 figure 65: program disable ........................................................................................................................ 81 figure 66: program for internal data move enable .............................................................................. 82 figure 67: program for internal data move disable ............................................................................. 82 figure 68: reset operation .......................................................................................................................... 92 figure 69: read status cycle ...................................................................................................................... 92 figure 70: read parameter page .............................................................................................................. 93 figure 71: read page .................................................................................................................................. 93 figure 72: read page operation with ce# dont care ................................................................................ 94 figure 73: random data read .................................................................................................................. 95 figure 74: read page cache sequential ................................................................................................. 96 figure 75: read page cache random ...................................................................................................... 97 figure 76: read id operation ....................................................................................................................... 98 figure 77: program page operation ........................................................................................................... 98 figure 78: program page operation with ce# dont care ........................................................................ 99 figure 79: program page operation with random data input .............................................................. 99 figure 80: program page cache .............................................................................................................. 100 figure 81: program page cache ending on 15h ....................................................................................... 100 figure 82: internal data move ............................................................................................................... 101 figure 83: erase block operation .............................................................................................................. 101 micron confidential and proprietary 1gb: x8, x16 nand flash memory pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
general description micron nand flash devices include an asynchronous data interface for high-perform- ance i/o operations. these devices use a highly multiplexed 8-bit bus (i/ox) to transfer commands, address, and data. there are five control signals used to implement the asyn- chronous data interface: ce#, cle, ale, we#, and re#. additional signals control hardware write protection and monitor device status (r/b#). this hardware interface creates a low pin-count device with a standard pinout that re- mains the same from one density to another, enabling future upgrades to higher densi- ties with no board redesign. a target is the unit of memory accessed by a chip enable signal. a target contains one or more nand flash die. a nand flash die is the minimum unit that can independently execute commands and report status. a nand flash die, in the onfi specification, is referred to as a logical unit (lun). there is at least one nand flash die per chip enable signal. for further details, see device and array organization. signal descriptions and assignments table 1: asynchronous signal definitions signal 1 type description 2 ale input address latch enable: loads an address from i/o[7:0] into the address register. ce# input chip enable: enables or disables one or more die (luns) in a target. cle input command latch enable: loads a command from i/o[7:0] into the command register. lock input when lock is high during power-up, the block lock function is enabled. to disable the block lock, connect lock to vss during power-up, or leave it disconnected (internal pull- down). re# input read enable: transfers serial data from the nand flash to the host system. we# input write enable: transfers commands, addresses, and serial data from the host system to the nand flash. wp# input write protect: enables or disables array program and erase operations. i/o[7:0] (x8) i/o[15:0] (x16) i/o data inputs/outputs: the bidirectional i/os transfer address, data, and command informa- tion. r/b# output ready/busy: an open-drain, active-low output that requires an external pull-up resistor. this signal indicates target array activity. v cc supply v cc : core power supply v ss supply v ss : core ground connection nc C no connect: ncs are not internally connected. they can be driven or left unconnected. dnu C do not use: dnus must be left unconnected. notes: 1. see device and array organization for detailed signal connections. 2. see asynchronous interface bus operations for detailed asynchronous interface signal descriptions. micron confidential and proprietary 1gb: x8, x16 nand flash memory general description pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 2: 48-pin tsop C type 1, cpl (top view) x8 nc nc nc nc nc nc r/b# re# ce# nc nc v cc v ss nc nc cle ale we# wp# nc nc nc nc nc x8 v ss 1 nc nc nc i/o7 i/o6 i/o5 i/o4 nc v cc 1 dnu v cc v ss nc v cc 1 nc i/o3 i/o2 i/o1 i/o0 nc nc nc v ss 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 note: 1. these pins might not be bonded in the package; however, micron recommends that the customer connect these pins to the designated external sources for onfi compatibility. micron confidential and proprietary 1gb: x8, x16 nand flash memory signal descriptions and assignments pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 3: 63-ball vfbga, x8 (balls down, top view) 3 wp# v cc 1 nc nc dnu nc nc v ss 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc 4 ale re# nc nc v cc 1 i/o0 i/o1 i/o2 8 r/b# nc nc nc nc v cc i/o7 v ss 10 nc nc nc nc 9 nc nc nc nc 5 v ss cle nc nc lock nc nc i/o3 7 we# nc nc v ss 1 nc nc i/o5 i/o6 6 ce# nc nc nc nc nc v cc i/o4 note: 1. these pins might not be bonded in the package; however, micron recommends that the customer connect these pins to the designated external sources for onfi compatibility. micron confidential and proprietary 1gb: x8, x16 nand flash memory signal descriptions and assignments pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 4: 63-ball vfbga, x16 (balls down, top view) 3 wp# v cc nc nc dnu i/o8 i/o9 v ss 4 ale re# nc nc v cc i/o0 i/o1 i/o2 8 r/b# nc nc nc nc v cc i/o7 v ss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc lock i/o10 i/o11 i/o3 7 we# nc nc v ss i/o15 i/o14 i/o5 i/o6 6 ce# nc nc nc i/o13 i/o12 v cc i/o4 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc micron confidential and proprietary 1gb: x8, x16 nand flash memory signal descriptions and assignments pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
package dimensions figure 5: 48-pin tsop C type 1, cpl 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. note: 1. all dimensions are in millimeters. micron confidential and proprietary 1gb: x8, x16 nand flash memory package dimensions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 6: 63-ball vfbga (hc) ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 96.5% sn, 3%ag, 0.5% cu 13.00 0.10 ball a10 ball a1 id 0.80 typ 0.80 typ 6.50 0.05 10.50 0.10 5.25 0.05 3.60 4.40 0.65 0.05 seating plane a 8.80 7.20 0.10 a ball a1 63x ?0.45 dimensions apply to solder balls post reflow. pre-reflow ball is ?0.42 on a ?0.4 smd ball pad. c l c l note: 1. all dimensions are in millimeters. micron confidential and proprietary 1gb: x8, x16 nand flash memory package dimensions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 7: 63-ball vfbga (h4) 9mm x 11mm ball a1 id seating plane 0.12 a a 0.65 0.05 1.0 max 0.25 min 9 0.1 ball a1 id 8.8 ctr solder ball material: sac305. dimensions apply to solder balls post- reflow on ?0.4 smd ball pads. a b c d e f g h j k l m 10 9 8 7 6 5 4 3 2 1 63x ?0.45 11 0.1 0.8 typ 0.8 typ 7.2 ctr note: 1. all dimensions are in millimeters. micron confidential and proprietary 1gb: x8, x16 nand flash memory package dimensions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control de- vice operations. the addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. data is transferred to or from the nand flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. the nand flash memory array is programmed and read using page-based operations and is erased using block-based operations. during normal page operations, the data and cache registers act as a single register. during cache operations, the data and cache registers operate independently to increase data throughput. the status register reports the status of die operations. figure 8: nand flash die (lun) functional block diagram address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# lock 1 i/ox control logic i/o control r/b# row decode column decode nand flash array note: 1. the lock pin is used on the 1.8v device. micron confidential and proprietary 1gb: x8, x16 nand flash memory architecture pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
device and array organization figure 9: array organization C x8 cache register data register 1024 blocks per device 1 block 64 2048 64 2048 2112 bytes i/o7 i/o0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 1024 blocks = 1056mb table 2: array addressing (x8) cycle i/o7 i/o6 i/o5 i/o4 i/oq3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 1 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 notes: 1. if ca11 is 1, then ca[10:6] must be 0. 2. block address concatenated with page address = actual page address; cax = column ad- dress; pax = page address; bax = block address. micron confidential and proprietary 1gb: x8, x16 nand flash memory device and array organization pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 10: array organization C x16 cache register data register 1024 blocks per device 1 block 32 1024 32 1024 1056 words i/o15 i/o0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 1024 blocks = 1056mb table 3: array addressing (x16) cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 1 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 notes: 1. if ca10 is 1, then ca[9:5] must be 0. 2. block address concatenated with page address = actual page address. cax = column ad- dress; pax = page address; bax = block address. 3. i/o[15:8] are not used during the addressing sequence and should be driven low. micron confidential and proprietary 1gb: x8, x16 nand flash memory device and array organization pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous interface bus operation the bus on the device is multiplexed. data i/o, addresses, and commands all share the same pins. i/o[15:8] are used only for data in the x16 configuration. addresses and com- mands are always supplied on i/o[7:0]. the command sequence normally consists of a command latch cycle, address input cycles, and one or more data cycleseither read or write. table 4: asynchronous interface mode selection mode ce# cle ale we# re# i/ox wp# notes standby h x x x x x 0v/v cc 1 command input l h l h x h address input l l h h x h data input l l l h x h data output l l l h x x write protect x x x x x x l notes: 1. wp# should be biased to cmos low or high for standby. 2. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . asynchronous enable/standby when the device is not performing an operation, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power con- sumption. the ce# dont care operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flash is busy with internal operations. this capability is important for designs that require multiple nand flash devices on the same bus. a high cle signal indicates that a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. asynchronous commands an asynchronous command is written from i/o[7:0] to the command register on the rising edge of we# when ce# is low, ale is low, cle is high, and re# is high. commands are typically ignored by die (luns) that are busy (rdy = 0); however, some commands, including read status (70h), are accepted by die (luns) even when they are busy. for devices with a x16 interface, i/o[15:8] must be written with zeros when a command is issued. micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 11: asynchronous command latch cycle we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls dont care micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous addresses an asynchronous address is written from i/o[7:0] to the address register on the rising edge of we# when ce# is low, ale is high, cle is low, and re# is high. bits that are not part of the address space must be low (see device and array organiza- tion.) the number of cycles required for each command varies. refer to the command descriptions to determine addressing requirements. addresses are input on i/o[7:0] on x8 devices and on i/o[15:0] on x16 devices. figure 12: asynchronous address latch cycle we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 dont care undefined t wc micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous data input data is written to the cache register of the selected die (lun) on the rising edge of we# when ce# is low, ale is low, cle is low, and re# is high. data input is ignored by die (luns) that are not selected or are busy (rdy = 0). data is written to the data register on the rising edge of we# when ce#, cle, and ale are low, and the device is not busy. data is input on i/o[7:0] on x8 devices and on i/o[15:0] on x16 devices. figure 13: asynchronous data input cycles we# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in m+1 d in n dont care t wc d in m micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous data output data can be output from a die (lun) if it is in a ready state. data output is supported following a read operation from the nand flash array. data is output from the cache register of the selected die (lun) on the falling edge of re# when ce# is low, ale is low, cle is low, and we# is high. if the host controller is using a t rc of 30ns or greater, the host can latch the data on the rising edge of re# (see for proper timing). if the host controller is using a t rc of less than 30ns, the host can latch the data on the next falling edge of re# (see (page 0 ) for extended data output (edo) timing). data is output on i/o[7:0] on x8 devices and on i/o[15:0] on x16 devices. figure 14: asynchronous data output cycles ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea dont care t rhz t chz t rhz t rhoh rdy t coh d out d out d out micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 15: asynchronous data output cycles (edo mode) d out d out d out ce# re# i/ox rdy t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz dont care write protect the write protect# (wp#) signal enables or disables program and erase operations to a target. when wp# is low, program and erase operations are disabled. when wp# is high, program and erase operations are enabled. it is recommended that the host drive wp# low during power-on until vcc is stable to prevent inadvertent program and erase operations (see device initialization (page 28) for additional details). wp# must be transitioned only when the target is not busy and prior to beginning a command sequence. after a command sequence is complete and the target is ready, wp# can be transitioned. after wp# is transitioned, the host must wait t ww before issu- ing a new command. the wp# signal is always an active input, even when ce# is high. this signal should not be multiplexed with other signals. ready/busy# the ready/busy# (r/b#) signal provides a hardware method of indicating whether a tar- get is ready or busy. a target is busy when one or more of its die (luns) are busy (rdy = 0). a target is ready when all of its die (luns) are ready (rdy = 1). because each die (lun) contains a status register, it is possible to determine the independent status of each die (lun) by polling its status register instead of using the r/b# signal (see sta- tus operations for details regarding die (lun) status). this signal requires a pull-up resistor, rp, for proper operation. r/b# is high when the target is ready, and transitions low when the target is busy. the signal's open-drain micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
driver enables multiple r/b# outputs to be or-tied. typically, r/b# is connected to an interrupt pin on the system controller. the combination of rp and capacitive loading of the r/b# circuit determines the rise time of the r/b# signal. the actual value used for rp depends on the system timing re- quirements. large values of rp cause r/b# to be delayed significantly. between the 10- to 90-percent points on the r/b# waveform, the rise time is approximately two time constants (tc). tc = r c where r = rp (resistance of pull-up resistor), and c = total capacitive load. the fall time of the r/b# signal is determined mainly by the output impedance of the r/b# signal and the total load capacitance. approximate rp values using a circuit load of 100pf are provided in figure 21 (page 27). the minimum value for rp is determined by the output drive capability of the r/b# signal, the output voltage swing, and v cc . rp = v cc (max) - v ol (max) i ol + il where il is the sum of the input currents of all devices tied to the r/b# pin. figure 16: read/busy# open drain rp v cc r/b# open drain output i ol v ss device micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 17: t fall and t rise (3.3v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 C1 0 2 4 0 2 4 6 t fall t rise v cc 3.3v tc v notes: 1. t fall and t rise calculated at 10% and 90% points. 2. t rise dependent on external capacitance and resistive loading and output transistor im- pedance. 3. t rise primarily dependent on external pull-up resistor and external capacitive loading. 4. t fall = 10ns at 3.3v 5. see tc values in figure 21 (page 27) for approximate rp value and tc. figure 18: t fall and t rise (1.8v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise v cc 1.8v tc v notes: 1. t fall and t rise are calculated at 10% and 90% points. 2. t rise is primarily dependent on external pull-up resistor and external capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 21 (page 27) for tc and approximate rp value. micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 19: i ol vs rp (v cc = 3.3v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 400 0 6000 8000 10,000 12,000 iol at vcc (max) rp ( ) i (ma) figure 20: i ol vs rp (1.8v v cc ) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000 rp ( ) i (ma) iol at vcc (max) micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 21: tc vs rp 1200 1000 800 600 400 200 0 0 2000 4000 6000 8000 10,000 12,000 iol at vcc (max) rc = tc c = 100pf rp ( ) t(ns) micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface bus operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
device initialization micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. (the wp# signal supports additional hardware protection during power transitions.) when ramping v cc , use the following procedure to initialize the device: 1. ramp v cc . 2. the host must wait for r/b# to be valid and high before issuing reset (ffh) to any target. the r/b# signal becomes valid when 50s has elapsed since the begin- ning the v cc ramp, and 10s has elapsed since v cc reaches v cc (min). 3. if not monitoring r/b#, the host must wait at least 100s after v cc reaches v cc (min). if monitoring r/b#, the host must wait until r/b# is high. 4. the asynchronous interface is active by default for each target. each lun draws less than an average of 10ma (i st ) measured over intervals of 1ms until the reset (ffh) command is issued. 5. the reset (ffh) command must be the first command issued to all targets (ce#s) after the nand flash device is powered on. each target will be busy for 1ms after a reset command is issued. the reset busy time can be monitored by polling r/ b# or issuing the read status (70h) command to poll the status register. 6. the device is now initialized and ready for normal operation. figure 22: r/b# power-on behavior reset (ffh) is issued 50s (min) 100s (max) invalid 10s (max) v cc ramp starts v cc r/b# v cc = v cc (min) micron confidential and proprietary 1gb: x8, x16 nand flash memory device initialization pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
command definitions table 5: command set command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 notes rest operations reset ffh 0 C C yes identification operations read id 90h 1 C C no 2 read parameter page ech 1 C C no read unique id edh 1 C C no feature operations get features eeh 1 C C no 2 set features efh 1 4 C no 3 status operations read status 70h 0 C C yes column address operations random data read 05h 2 C e0h no random data input 85h 2 optional C no program for internal data move 85h 4 optional C no read operations read mode 00h 0 C C no read page 00h 4 C 30h no read page cache sequential 31h 0 C C no 4 read page cache random 00h 4 C 31h no 4 read page cache last 3fh 0 C C no 4 program operations program page 80h 4 yes 10h no program page cache 80h 4 yes 15h no 5 erase operations erase block 60h 2 C d0h no internal data move operations read for internal data move 00h 4 C 35h no program for internal data move 85h 4 optional 10h no boot block operations micron confidential and proprietary 1gb: x8, x16 nand flash memory command definitions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 5: command set (continued) command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 notes boot block protect 80h 4 yes 10h no 6 block lock operations block unlock low 23h 2 C C no block unlock high 24h 2 C C no block lock 2ah C C C no block lock-tight 2ch C C C no block lock read status 7ah 2 C C no one-time programmable (otp) operations otp data lock by page (onfi) 80h 4 no 10h no 7, 8 otp data program (onfi) 80h 4 yes 10h no 7, 8 otp data read (onfi) 00h 4 no 30h no 7, 8 notes: 1. busy means rdy = 0. 2. the read id (90h) and get features (eeh) output identical data on rising and falling dqs edges. 3. the set features (efh) command requires data transition prior to the rising edge of clk, with identical data for the rising and falling edges. 4. issuing a read page cache-series (31h, 00h-31h, 00h-32h, 3fh) command when the ar- ray is busy (rdy = 1, ardy = 0) is supported if the previous command was a read page (00h-30h) or read page cache-series command; otherwise, it is prohibited. 5. issuing a program page cache (80h-15h) command when the array is busy (rdy = 1, ardy = 0) is supported if the previous command was a program page cache (80h-15h) command; otherwise, it is prohibited. 6. the boot block protect command can only be issued after issuing the set features command with the feature address. 7. read page cache sequential is not supported on otp pages. 8. otp commands can be entered only after issuing the set features command with the feature address. micron confidential and proprietary 1gb: x8, x16 nand flash memory command definitions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
reset operations reset (ffh) the reset command is used to put the memory device into a known condition and to abort the command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partially erased or programmed, and is inva- lid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register. the reset command must be issued to all ce#s as the first command after power-on. the device will be busy for a maximum of 1ms. figure 23: reset (ffh) operation cycle type i/o[7:0] r/b# t rst t wb ff command micron confidential and proprietary 1gb: x8, x16 nand flash memory reset operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
identification operations read id (90h) the read id (90h) command is used to read identifier codes programmed into the tar- get. this command is accepted by the target only when all die (luns) on the target are idle. writing 90h to the command register puts the target in read id mode. the target stays in this mode until another valid command is issued. when the 90h command is followed by an 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer id, device configuration, and part-specif- ic information. when the 90h command is followed by a 20h address cycle, the target returns the 4-byte onfi identifier code. figure 24: read id (90h) with 00h address operation cycle type i/o[7:0] t whr command 90h 00h byte 0 byte 1 byte 2 byte 3 address d out d out d out d out d out byte 4 note: 1. see the read id parameter tables for byte definitions. figure 25: read id (90h) with 20h address operation cycle type i/o[7:0] t whr command 90h 20h 4fh 4eh 46h 49h address d out d out d out d out note: 1. see read id parameter tables for byte definitions. micron confidential and proprietary 1gb: x8, x16 nand flash memory identification operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read id parameter tables table 6: read id parameters for address 00h options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 byte 0 C manufacturer id manufacturer micron 0 0 1 0 1 1 0 0 2ch byte 1 C device id mt29f1g08aac 1gb, x8, 3.3v 1 1 1 1 0 0 0 1 f1h mt29f1g08abc 1gb, x8, 1.8v 1 0 1 0 0 0 0 1 a1h mt29f1g16abc 1gb, x16, 1.8v 1 0 1 1 0 0 0 1 b1h byte 2 number of die per ce 1 0 0 00b cell type slc 0 0 00b number of simultaneously program- med pages 1 0 0 00b interleaved operations between multiple die not supported 0 0b cache programming supported 1 1b byte value mt29f1g08aac 1gb, x8, 3.3v 1 0 0 0 0 0 0 0 80h mt29f1g08abc 1gb, x8, 1.8v 1 0 0 0 0 0 0 0 80h mt29f1g16abc 1gb, x16, 1.8v 1 0 0 0 0 0 0 0 80h byte 3 page size 2kb 0 1 01b spare area size (bytes) 64b 1 1b block size (w/o spare) 128kb 0 1 01b organization 1gb, x8, 3.3v, 1.8v 0 0b 1gb, x16, 1.8v 1 1b serial access (min) 35ns (1.8v) 0 0 0xxx0b 25ns (3.3v) 1 0 1xxx0b byte value mt29f1g08aac 1 0 0 1 0 1 0 1 95h mt29f1g08abc 0 0 0 1 0 1 0 1 15h mt29f1g16abc 0 1 0 1 0 1 0 1 55h byte 4 reserved 0 0 00b planes per ce# 1 0 0 00b plane size 1gb 0 0 0 000b reserved 0 0b byte value 3.3v 0 0 0 0 0 0 0 0 00h 1.8v 0 0 0 0 0 0 0 0 00h note: 1. b = binary; h = hexadecimal. micron confidential and proprietary 1gb: x8, x16 nand flash memory read id parameter tables pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 7: read id parameters for address 20h byte options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 0 o 0 1 0 0 1 1 1 1 4fh 1 n 0 1 0 0 1 1 1 0 4eh 2 f 0 1 0 0 0 1 1 0 46h 3 i 0 1 0 0 1 0 0 1 49h note: 1. h = hexadecimal. micron confidential and proprietary 1gb: x8, x16 nand flash memory read id parameter tables pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read parameter page (ech) the read parameter page (ech) command is used to read the onfi parameter page programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing ech to the command register puts the target in read parameter page mode. the target stays in this mode until another valid command is issued. when the ech command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. a minimum of three copies of the parameter page are stored in the device. each param- eter page is 256 bytes. if desired, the random data read (05h-e0h) command can be used to change the location of data output. figure 26: read parameter (ech) operation cycle type i/o[7:0] r/b# t wb t r t rr command address d out ech 00h p0 0 p1 0 d out d out p0 1 d out d out p1 1 d out micron confidential and proprietary 1gb: x8, x16 nand flash memory read parameter page (ech) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
parameter page data structure tables table 8: parameter page data structure byte description value 0C3 parameter page signature 4fh, 4eh, 46h, 49h 4C5 revision number 02h, 00h 6C7 features supported mt29f1g08abc 10h, 00h mt29f1g16abc 11h, 00h mt29f1g08aac 8C9 optional commands supported 3fh, 00h 10C31 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 32C43 device manufacturer 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h 44C63 device model mt29f1g08abc 4dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h, 42h, 43h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f1g16abc 4dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h, 42h, 43h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f1g08aac 4dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h, 41h, 43h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 manufacturer id 2ch 65C66 date code 00h,00h 67C79 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80C83 number of data bytes per page 00h, 08h, 00h, 00h 84C85 number of spare bytes per page 40h, 00h 86C89 number of data bytes per partial page 00h, 02h, 00h, 00h 90C91 number of spare bytes per partial page 10h, 00h 92C95 number of pages per block 40h, 00h, 00h, 00h 96C99 number of blocks per unit 00h, 04h, 00h, 00h 100 number of logical units 01h 101 number of address cycles 22h 102 number of bits per cell 01h 103C104 bad blocks maximum per unit 14h, 00h 105C106 block endurance 01h, 05h 107 guaranteed valid blocks at beginning of target 01h 108C109 block endurance for guaranteed valid blocks 00h, 00h 110 number of programs per page 04h 111 partia lprogramming attributes 00h 112 number of ecc bits 01h 113 number of interleaved address bits 00h 114 interleaved operation attributes 00h micron confidential and proprietary 1gb: x8, x16 nand flash memory parameter page data structure tables pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 8: parameter page data structure (continued) byte description value 115C127 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 128 i/o pin capacitance 0ah 129C130 timing mode support mt29f1g08abc 07h, 00h mt29f1g16abc 07h, 00h mt29f1g08aac 1fh, 00h 131C132 program cache timing mt29f1g08abc 07h, 00h mt29f1g16abc 07h, 00h mt29f1g08aac 1fh, 00h 133C134 t prog maximum page program time bch, 02h 135C136 t bers maximum block erase time b8h, 0bh 137C138 t r maximum page read time 19h, 00h 139C140 t ccs minimum mt29f1g08abc 64h, 00h mt29f1g16abc 64h, 00h mt29f1g08aac 46h, 00h 141C163 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 164C165 vendor-specific revision number 01h, 00h 166C253 vendor specific 00h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 02h, 02h, 01h, 1eh, 90h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 254C255 integrity crc set at shipment 256C511 value of bytes 0C255 512C767 value of bytes 0C255 768+ additional redundant parameter pages micron confidential and proprietary 1gb: x8, x16 nand flash memory parameter page data structure tables pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read unique id (edh) the read unique id (edh) command is used to read a unique identifier programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing edh to the command register puts the target in read unique id mode. the tar- get stays in this mode until another valid command is issued. when the edh command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. after t r completes, the host enables data output mode to read the unique id. when the asynchronous interface is active, one data byte is output per re# toggle. sixteen copies of the unique id data are stored in the device. each copy is 32 bytes. the first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple- ment of the first 16 bytes. the host should xor the first 16 bytes with the second 16 bytes. if the result is 16 bytes of ffh, then that copy of the unique id data is correct. in the event that a non-ffh result is returned, the host can repeat the xor operation on a subsequent copy of the unique id data. if desired, the random data read (05h-e0h) command can be used to change the data output location. the upper eight i/os on a x16 device are not used and are a dont care for x16 devices. figure 27: read unique id (edh) operation cycle type i/o[7:0] r/b# t wb t r t rr command address d out edh 00h u0 0 u1 0 d out d out u0 1 d out d out u1 1 d out micron confidential and proprietary 1gb: x8, x16 nand flash memory read unique id (edh) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
feature operations the set features (efh) and get features (eeh) commands are used to modify the target's default power-on behavior. these commands use a one-byte feature address to determine which subfeature parameters will be read or modified. each feature address (in the 00h to ffh range) is defined in below. the set features (efh) command writes subfeature parameters (p1Cp4) to the specified feature address. the get fea- tures command reads the subfeature parameters (p1Cp4) at the specified feature address. table 9: feature address definitions feature address definition 00h reserved 01h timing mode 02hC7fh reserved 80h programmable output drive strength 81h programmable rb# pull-down strength 82hCffh reserved 90h array operation mode (1.8v only) set features (efh) the set features (efh) command writes the subfeature parameters (p1Cp4) to the specified feature address to enable or disable target-specific features. this command is accepted by the target only when all die (luns) on the target are idle. writing efh to the command register puts the target in the set features mode. the tar- get stays in this mode until another command is issued. the efh command is followed by a valid feature address as specified in . the host waits for t adl before the subfeature parameters are input. when the asynchronous interface is active, one subfeature parameter is latched per rising edge of we#. after all four subfeature parameters are input, the target goes busy for t feat. the read status (70h) command can be used to monitor for command completion. feature address 01h (timing mode) operation is unique. if set features is used to modify the interface type, the target will be busy for t itc. figure 28: set features (efh) operation cycle type i/o[7:0] r/b# t adl command address efh fa d in d in d in d in p1 p2 p3 p4 t wb t feat micron confidential and proprietary 1gb: x8, x16 nand flash memory feature operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
get features (eeh) the get features (eeh) command reads the subfeature parameters (p1Cp4) from the specified feature address. this command is accepted by the target only when all die (luns) on the target are idle. writing eeh to the command register puts the target in get features mode. the target stays in this mode until another valid command is issued. when the eeh command is followed by a feature address, the target goes busy for t feat. if the read status (70h) command is used to monitor for command comple- tion, the read mode (00h) command must be used to re-enable data output mode. after t feat completes, the host enables data output mode to read the subfeature param- eters. figure 29: get features (eeh) operation cycle type i/ox r/b# t wb t feat t rr command address d out eeh fa p1 p2 d out d out p3 p4 d out micron confidential and proprietary 1gb: x8, x16 nand flash memory feature operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 10: feature addresses 01h: timing mode subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 timing mode mode 0 (default) reserved (0) 0 0 0 00h 1, 2 mode 1 reserved (0) 0 0 1 01h 2 mode 2 reserved (0) 0 1 0 02h 2 mode 3 reserved (0) 0 1 1 03h 3 mode 4 reserved (0) 1 0 0 04h 3 mode 5 reserved (0) 1 0 1 05h 4 p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h notes: 1. the timing mode feature address is used to change the default timing mode. the timing mode should be selected to indicate the maximum speed at which the device will re- ceive commands, addresses, and data cycles. the five supported settings for the timing mode are shown. the default timing mode is mode 0. the device returns to mode 0 when the device is power cycled. supported timing modes are reported in the parame- ter page. 2. supported for both 1.8v and 3.3v. 3. supported for 3.3v only. 4. not supported. micron confidential and proprietary 1gb: x8, x16 nand flash memory feature operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 11: feature addresses 80h: programmable i/o drive strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 i/o drive strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h note: 1. the programmable drive strength feature address is used to change the default i/o drive strength. drive strength should be selected based on expected loading of the mem- ory bus. this table shows the four supported output drive strength settings. the default drive strength is full strength. the device returns to the default drive strength mode when the device is power cycled. ac timing parameters may need to be relaxed if i/o drive strength is not set to full. table 12: feature addresses 81h: programmable r/b# pull-down strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 r/b# pull-down strength full (default) 0 0 00h 1 three-quarters 0 1 01h one-half 1 0 02h one-quarter 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h note: 1. this feature address is used to change the default r/b# pull-down strength. its strength should be selected based on the expected loading of r/b#. full strength is the default, power-on value. micron confidential and proprietary 1gb: x8, x16 nand flash memory feature operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 13: features address 90h: operation mode note: these bits are reset to 00h on power cycle. subfeature parameter options i/o7 i/o6 i/05 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 operation mode opera- tion normal reserved (0) 0 00h 1 otp opera- tion reserved (0) 1 01h otp protec- tion reserved (0) 1 1 03h boot block lock reserved (0) 1 0 0 04h p2 reserved reserved (0) 00h p3 reserved reserved (0) 00h p4 reserved reserved (0) 00h micron confidential and proprietary 1gb: x8, x16 nand flash memory feature operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
status operations each die (lun) provides its status independently of other die (luns) on the same tar- get through its 8-bit status register. after the read status (70h) command is issued, status register output is enabled. the contents of the status register are returned on i/o[7:0] for each data output request. when the asynchronous interface is active and status register output is enabled, changes in the status register are seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to toggle re# to see the status register update. while monitoring the status register to determine when a data transfer from the flash array to the data register ( t r) is complete, the host must issue the read mode (00h) command to disable the status register and enable data output (see read operations). table 14: status register definition sr bit program page program page cache mode page read page read cache mode block erase description 7 write protect write protect write protect write protect write protect 0 = protected 1 = not protected 6 rdy rdy 2 cache rdy rdy 2 cache rdy 0 = busy 1 = ready 5 ardy ardy 1 ardy ardy 1 ardy 0 = busy 1 = ready 4 C C C C C reserved (0) 3 C C C C C reserved (0) 2 C C C C C reserved (0) 1 C failc (nC1) C C C 0 = pass 1 = fail 0 fail fail (n) C C fail 0 = pass 1 = fail notes: 1. status register bit 5 is 0 during the actual programming operation. if cache mode is used, this bit will be 1 when all internal operations are complete. 2. status register bit 6 is 1 when the cache is ready to accept new data. r/b# follows bit 6. micron confidential and proprietary 1gb: x8, x16 nand flash memory status operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read status (70h) the read status (70h) command returns the status of the last-selected die (lun) on a target. this command is accepted by the last-selected die (lun) even when it is busy (rdy = 0). if there is only one die (lun) per target, the read status (70h) command can be used to return status following any nand command. figure 30: read status (70h) operation cycle type i/o[7:0] t whr command d out 70h sr micron confidential and proprietary 1gb: x8, x16 nand flash memory status operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
column address operations the column address operations affect how data is input to and output from the cache registers within the selected die (luns). these features provide host flexibility for man- aging data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. when the asynchronous interface is active, column address operations can address any byte in the selected cache register. random data read (05h-e0h) the random data read (05h-e0h) command changes the column address of the se- lected cache register and enables data output from the last selected die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache read operations (rdy = 1; ardy = 0). writing 05h to the command register, followed by two column address cycles contain- ing the column address, followed by the e0h command, puts the selected die (lun) into data output mode. after the e0h command cycle is issued, the host must wait at least t whr before requesting data output. the selected die (lun) stays in data output mode until another valid command is issued. figure 31: random data read (05h-e0h) operation cycle type i/o[7:0] sr[6] command address address 05h command e0h c1 c2 t whr t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1 micron confidential and proprietary 1gb: x8, x16 nand flash memory column address operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
random data input (85h) the random data input (85h) command changes the column address of the selec- ted cache register and enables data input on the last-selected die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache program operations (rdy = 1; ardy = 0). writing 85h to the command register, followed by two column address cycles contain- ing the column address, puts the selected die (lun) into data input mode. after the second address cycle is issued, the host must wait at least t adl before inputting data. the selected die (lun) stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the random data input (85h) command is allowed after the required address cy- cles are specified, but prior to the final command cycle of the following commands while data input is permitted: program page (80h-10h), program page cache (80h-15h), and program for internal data move (85h-10h). figure 32: random data input (85h) operation cycle type i/o[7:0] rdy command address address 85h c1 c2 t adl d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 as defined for page (cache) program as defined for page (cache) program micron confidential and proprietary 1gb: x8, x16 nand flash memory column address operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
program for internal data input (85h) the program for internal data input (85h) command changes the row address (block and page) where the cache register contents will be programmed in the nand flash array. it also changes the column address of the selected cache register and ena- bles data input on the specified die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache programming operations (rdy = 1; ardy = 0). write 85h to the command register. then write two column address cycles and three row address cycles. this updates the page and block destination of the selected device for the addressed lun and puts the cache register into data input mode. after the fifth address cycle is issued the host must wait at least t adl before inputting data. the selec- ted lun stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the program for internal data input (85h) command is allowed after the re- quired address cycles are specified, but prior to the final command cycle of the follow- ing commands while data input is permitted: program page (80h-10h), program page cache (80h-15h), and program for internal data move (85h-10h). when used with these commands, the lun address and device select bits are required to be identical to the lun address and device select bits originally specified. the program for internal data input (85h) command enables the host to mod- ify the original page and block address for the data in the cache register to a new page and block address. in devices that have more than one die (lun) per target, the program for inter- nal data input (85h) command can be used with other commands that support interleaved die (multi-lun) operations. the program for internal data input (85h) command can be used with the ran- dom data read (05h-e0h) command to read and modify cache register contents in small sections prior to programming cache register contents to the nand flash array. this capability can reduce the amount of buffer memory used in the host controller. the random data input (85h) command can be used during the program for internal data move command sequence to modify one or more bytes of the origi- nal data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (85h) command is written along with the address of the data to be modified next. new data is input on the external data pins. this copies the new data into the cache register. micron confidential and proprietary 1gb: x8, x16 nand flash memory column address operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 33: program for internal data input (85h) operation cycle type i/o[7:0] rdy command address address address address 85h c1 c2 t adl d in dk d in dk + 1 d in dk + 2 din dn din dn + 1 as defined for page (cache) program as defined for page (cache) program r1 r2 micron confidential and proprietary 1gb: x8, x16 nand flash memory column address operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read operations the read page (00h-30h) command, when issued by itself, reads one page from the nand flash array to its cache register and enables data output for that cache register. during data output the following commands can be used to read and modify the data in the cache registers: random data read (05h-e0h) and random data input (85h). read cache operations to increase data throughput, the read page cache series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the nand flash array to the data register. to begin a read page cache sequence, begin by reading a page from the nand flash array to its corresponding cache register using the read page (00h-30h) command. r/b# goes low during t r and the selected die (lun) is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), issue either of these commands: ? read page cache sequential (31h) C copies the next sequential page from the nand flash array to the data register ? read page cache random (00h-31h) C copies the page specified in this command from the nand flash array to its corresponding data register after the read page cache series (31h, 00h-31h) command has been issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the next page begins copying data from the array to the data register. after t rcbsy, r/b# goes high and the dies (luns) status register bits indicate the device is busy with a cache operation (rdy = 1, ardy = 0). the cache register becomes available and the page requested in the read page cache operation is transferred to the data regis- ter. at this point, data can be output from the cache register, beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data output by the die (lun). after outputting the desired number of bytes from the cache register, either an addition- al read page cache series (31h, 00h-31h) operation can be started or the read page cache last (3fh) command can be issued. if the read page cache last (3fh) command is issued, r/b# goes low on the tar- get, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the data register is copied into the cache register. after t rcbsy, r/b# goes high and rdy = 1 and ardy = 1, indicating that the cache register is available and that the die (lun) is ready. data can then be output from the cache register, beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output. for read page cache series (31h, 00h-31h, 3fh), during the die (lun) busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h) and reset (ffh). when rdy = 1 and ardy = 0, the only valid commands during read page cache series (31h, 00h-31h) operations are status operations (70h), read mode (00h), read page cache series (31h, 00h-31h), random data read (05h- e0h), and reset (ffh). micron confidential and proprietary 1gb: x8, x16 nand flash memory read operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read mode (00h) the read mode (00h) command disables status output and enables data output for the last-selected die (lun) and cache register after a read operation (00h-30h, 00h-3ah, 00h-35h) has been monitored with a status operation (70h, 78h). this com- mand is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). read page (00h-30h) the read page (00hC30h) command copies a page from the nand flash array to its respective cache register and enables data output. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to read a page from the nand flash array, write the 00h command to the command register, then write n address cycles to the address registers, and conclude with the 30h command. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. if the status opera- tions are used to monitor the lun's status, when the die (lun) is ready (rdy = 1, ardy = 1), the host disables status output and enables data output by issuing the read mode (00h) command. when the host requests data output, output begins at the column address specified. during data output the random data read (05h-e0h) command can be issued. figure 34: read page (00h-30h) operation cycle type i/o[7:0] rdy command address address address address command t wb t r t rr 00h c1 c2 r1 r2 30h d out d n d out d n + 1 d out d n + 2 read page cache sequential (31h) the read page cache sequential (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 31h to the command register. after this command is is- sued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point, data can micron confidential and proprietary 1gb: x8, x16 nand flash memory read operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
be output from the cache register beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output from the cache register. the read page cache sequential (31h) command can be used to cross block boun- daries. if the read page cache sequential (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in which the 31h command was issued. do not issue the read page cache se- quential (31h) to cross die (lun) boundaries. instead, issue the read page cache last (3fh) command. figure 35: read page cache sequential (31h) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command d out d out d out command d out 31h rr t wb command 30h t wb t rcbsy t rr d0 d n 31h d0 command address x4 00h page address m page m page m+1 t r micron confidential and proprietary 1gb: x8, x16 nand flash memory read operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read page cache random (00h-31h) the read page cache random (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 00h to the command register, then write n address cycles to the address register, and conclude by writing 31h to the command register. the col- umn address in the address specified is ignored. the die (lun) address must match the same die (lun) address as the previous read page (00h-30h) command or, if applica- ble, the previous read page cache random (00h-31h) command. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point, data can be output from the cache register beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output from the cache register. figure 36: read page cache random (00h-31h) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command d out d out d out 31h t rr t wb command 30h d0 d n command address x4 00h command 00h page address m address x4 page address n command 00h page m t r 1 cycle type i/o[7:0] rdy d out command d out t wb t rcbsy t rr d n 31h d0 command 00h address x4 page address p page n 1 micron confidential and proprietary 1gb: x8, x16 nand flash memory read operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
read page cache last (3fh) the read page cache last (3fh) command ends the read page cache sequence and copies a page from the data register to the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue the read page cache last (3fh) command, write 3fh to the command reg- ister. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is ready (rdy = 1, ardy = 1). at this point, data can be output from the cache register, beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output from the cache register. figure 37: read page cache last (3fh) operation cycle type i/o[7:0] rdy t wb t rcbsy t rr command command d out d out d out d out d out d out 31h t wb t rcbsy t rr d0 d0 d n as defined for read page cache (sequential or random) d n 3fh page n page address n micron confidential and proprietary 1gb: x8, x16 nand flash memory read operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
program operations program operations are used to move data from the cache or data registers to the nand array. during a program operation the contents of the cache and/or data regis- ters are modified by the internal control logic. within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (0, 1, 2, .., 63). during a program opera- tion, the contents of the cache and/or data registers are modified by the internal control logic. program operations the program page (80h-10h) command programs one page from the cache register to the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that the operation has completed successfully. program cache operations the program page cache (80h-15h) command can be used to improve program op- eration system performance. when this command is issued, the die (lun) goes busy (rdy = 0, ardy = 0) while the cache register contents are copied to the data register, and the die (lun) is busy with a program cache operation (rdy = 1, ardy = 0. while the contents of the data register are moved to the nand flash array, the cache register is available for an additional program page cache (80h-15h) or program page (80h-10h) command. for program page cache series (80h-15h) operations, during the die (lun) busy times, t cbsy and t lprog, when rdy = 0 and ardy = 0, the only valid commands are status operation (70h) and reset (ffh). when rdy = 1 and ardy = 0, the only valid com- mands during program page cache series (80h-15h) operations are status opera- tion (70h), program page cache (80h-15h), program page (80h-10h), random data input (85h), program for internal data input (85h), and reset (ffh). program page (80h-10h) the program page (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page ad- dress in the array of the selected die (lun). this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) when it is busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register and move it to the nand array at the block and page address specified, write 80h to the command register. issuing the 80h to the com- mand register clears all of the cache registers' contents on the selected target. write n address cycles containing the column address and row address. data input cycles fol- low. serial data is input beginning at the column address specified. at any time during the data input cycle the random data input (85h) and program for internal data input (85h) commands may be issued. when data input is complete, write 10h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t prog as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operation (70h) may be used. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit. micron confidential and proprietary 1gb: x8, x16 nand flash memory program operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 38: program page (80h-10h) operaton cycle type i/o[7:0] rdy t adl command address address address address 80h command 10h command 70h c1 c2 r1 r2 d in d in d in d in d0 d1 dn d out status t wb t prog program page cache (80h-15h) the program page cache (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (lun). after the data is copied to the data register, the cache register is avail- able for additional program page cache (80h-15h) or program page (80h-10h) commands. the program page cache (80h-15h) command is accepted by the die (lun) when it is ready (rdy =1, ardy = 1). it is also accepted by the die (lun) when busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register to move it to the nand array at the block and page address specified, write 80h to the command register. issuing the 80h to the command register clears all of the cache registers' contents on the selected target. then write n address cycles containing the column address and row address. data input cycles fol- low. serial data is input beginning at the column address specified. at any time during the data input cycle the random data input (85h) and program for internal data input (85h) commands may be issued. when data input is complete, write 15h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t cbsy to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data reg- ister, and then to begin moving the data register contents to the specified page and block address. to determine the progress of t cbsy, the host can monitor the target's r/b# signal or, alternatively, the status operation (70h) can be used. when the luns status shows that it is busy with a program cache operation (rdy = 1, ardy = 0), the host should check the status of the failc bit to see if a previous cache operation was successful. if, after t cbsy, the host wants to wait for the program cache operation to complete, with- out issuing the program page (80h-10h) command, the host should monitor ardy until it is 1. the host should then check the status of the fail and failc bits. micron confidential and proprietary 1gb: x8, x16 nand flash memory program operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 39: program page cache (80h-15h) operation (start) cycle type i/o[7:0] rdy t adl command address address address address 80h c1 c2 r1 r2 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type i/o[7:0] rdy t adl command address address address address 80h c1 c2 r1 r2 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy figure 40: program page cache (80h-15h) operation (end) cycle type i/o[7:0] rdy t adl command address address address address 80h c1 c2 r1 r2 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type rdy t adl command address as defined for page cache program address address address 80h c1 c2 r1 r2 d in d in d in d in command d0 d1 dn 10h 1 t wb t lprog i/o[7:0] micron confidential and proprietary 1gb: x8, x16 nand flash memory program operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
erase operations erase operations are used to clear the contents of a block in the nand flash array to prepare its pages for program operations. erase operations the erase block (60h-d0h) command erases one block in the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. erase block (60h-d0h) the erase block (60h-d0h) command erases the specified block in the nand flash array. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to erase a block, write 60h to the command register. then write two address cycles con- taining the row address; the page address is ignored. conclude by writing d0h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t bers while the block is erased. to determine the progress of an erase operation, the host can monitor the target's r/ b# signal, or alternatively, the status operation (70h) can be used. when the die (lun) is ready (rdy = 1, ardy = 1) the host should check the status of the fail bit. figure 41: erase block (60h-d0h) operation cycle type i/o[7:0] rdy command address address 60h command d1h r1 command address 60h ... r2 t wb t dbsy micron confidential and proprietary 1gb: x8, x16 nand flash memory erase operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
internal data move operations internal data move operations make it possible to transfer data within a device from one page to another using the cache register. this is particularly useful for block man- agement and wear leveling. the internal data move operation is a two-step process consisting of a read for internal data move (00h-35h) and a program for internal data move (85h-10h) command. to move data from one page to another, first issue the read for internal data move (00h-35h) command. when the die (lun) is ready (rdy = 1, ardy = 1), the host can transfer the data to a new page by issuing the program for internal data move (85h-10h) command. when the die (lun) is again ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation comple- ted successfully. to prevent bit errors from accumulating over multiple internal data move opera- tions, it is recommended that the host read the data out of the cache register after the read for internal data move (00h-35h) completes and prior to issuing the pro- gram for internal data move (85h-10h) command. the random data read (05h-e0h) command can be used to change the column address. the host should check the data for ecc errors and correct them. when the program for internal data move (85h-10h) command is issued, any corrected data can be input. the program for internal data input (85h) command can be used to change the column address. between the read for internal data move (00h-35h) and program for inter- nal data move (85h-10h) commands, the following commands are supported: status operation (70h) and column address operations (05h-e0h, 85h). the reset operation (ffh) can be issued after read for internal data move (00h-35h), but the con- tents of the cache registers on the target are not valid. read for internal data move (00h-35h) the read for internal data move (00h-35h) command is functionally identical to the read page (00h-30h) command, except that 35h is written to the command reg- ister instead of 30h. though it is not required, it is recommended that the host read the data out of the de- vice to verify the data prior to issuing the program for internal data move (85h-10h) command to prevent the propagation of data errors. micron confidential and proprietary 1gb: x8, x16 nand flash memory internal data move operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 42: read for internal data move (00h-35h) operation cycle type i/o[7:0] rdy command address address address address command t wb t r t rr 00h c1 c2 r1 r2 35h d out dn d out dn + 1 d out dn + 2 figure 43: read for internal data move (00h-35h) with random data read (05h-e0h) cycle type i/o[7:0] rdy command address address address address command t wb t r t rr 00h c1 c2 r1 r2 35h 1 cycle type i/o[7:0] rdy command address address command t whr 05h c1 c2 e0h d0 dk dj + n dk + 1 dk + 2 1 d out d out d out d out d out d out micron confidential and proprietary 1gb: x8, x16 nand flash memory internal data move operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
program for internal data move (85h-10h) the program for internal data move (85h-10h) command is functionally iden- tical to the program page (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. figure 44: program for internal data move (85h-10h) cycle type i/o[7:0] rdy command address address address address command t wb t prog 85h c1 c2 r1 r2 10h figure 45: program for internal data move (85h-10h) with random data input (85h) cycle type i/o[7:0] rdy command address address address address t wb t prog 85h c1 c2 r1 r2 1 cycle type i/o[7:0] rdy command address address t whr t whr 85h command 10h c1 c2 d in di dj d in d in di + 1 d in dj + 1 d in dj + 2 1 micron confidential and proprietary 1gb: x8, x16 nand flash memory internal data move operations pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
boot blocks this device provides up to four securable blocks (0, 1, 2, 3) that can be used to store critical information or boot code. normal program/erase and cache operations (except program page cache mode) are supported on the boot blocks. after the boot blocks are protected, no further program/erase operations can be issued to these blocks. the internal data move and program page cache mode are not supported on boot blocks. protecting the boot blocks protect the boot blocks by entering the boot block protect mode. to set up the device and enter the protect mode, issue the set features (efh) command to 90h (feature address) and write 04h to p1, followed by three cycles of 00h to p2Cp4. to protect the block, issue the 80h command followed by four address cycles (00h-00h- block address-00h), one data cycle of 00h, and then the 10h command. r/b# goes low for t roh. after the device is protected, it cannot be unprotected. micron confidential and proprietary 1gb: x8, x16 nand flash memory boot blocks pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
block lock feature the block lock feature protects either the entire device or ranges of blocks from being programmed and erased. using the block lock feature is preferable to using wp# to pre- vent program and erase operations. block lock is enabled and disabled at power-on through the lock pin. at power-on, if lock is low, all block lock commands are disabled. however if lock is high at power- on, the block lock commands are enabled and, by default, all the blocks on the device are protected, or locked, from program and erase operations, even if wp# is high. before the contents of the device can be modified, the device must first be unlocked. either a range of blocks or the entire device may be unlocked. program and erase operations complete successfully only in the block ranges that have been unlocked. blocks, once unlocked, can be locked again to protect them from further program and erase operations. blocks that are locked can be protected further, or locked tight. when locked tight, the devices blocks can no longer be locked or unlocked until the device is power cycled. wp# and block lock the following is true when the block lock feature is enabled: ? holding wp# low locks all blocks, provided the blocks are not locked tight. ? if wp# is held low to lock blocks, then returned to high, a new unlock command must be issued to unlock blocks. unlock (23h-24h) by default at power-on, if lock is high, all the blocks are locked and protected from program and erase operations. the unlock (23h) command is used to unlock a range of blocks. (unlocked blocks have no protection and can be programmed or erased.) the unlock command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. when the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. when the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boun- dary address registers are unlocked. the lower boundary block address must be less than the upper boundary block address. the following figures show examples of how the lower and upper boundary address registers work with the invert area bit. to unlock a range of blocks, issue the unlock (23h) command followed by the appro- priate address cycles that indicate the lower boundary block address. then issue the 24h command followed by the appropriate address cycles that indicate the upper boun- dary block address. the least significant page address bit, pa0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. the other page address bits should be 0. only one range of blocks can be specified in the lower and upper boundary block ad- dress registers. if after unlocking a range of blocks the unlock command is again issued, the new block address range determines which blocks are unlocked. the previ- ous unlocked block address range is not retained. micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 46: flash array protected: invert area bit = 0 block 1023 block 1022 block 1021 block 1020 block 1019 block 1018 block 1017 block 1016 block 1015 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 3fch 3f8h unprotected area protected area protected area upper block boundary lower block boundary figure 47: flash array protected: invert area bit = 1 3fch 3f8h protected area upper block boundary lower block boundary unprotected area unprotected area block 1023 block 1022 block 1021 block 1020 block 1019 block 1018 block 1017 block 1016 block 1015 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 15: block lock address cycle assignments ale cycle i/o[15:8] 1 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ba7 ba6 low low low low low invert area bit 2 second low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 notes: 1. i/o[15:8] is applicable only for x16 devices. 2. invert area bit is applicable for 24h command; it may be low or high for 23h command. figure 48: unlock operation unlock lower boundary upper boundary cle ce# we# ale re# i/ox 23h 24h block add 1 block add 2 block add 1 block add 2 micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
lock (2ah) by default at power-on, if lock is high, all the blocks are locked and protected from program and erase operations. if portions of the device are unlocked using the un- lock (23h) command, they can be locked again using the lock (2ah) command. the lock command locks all of the blocks in the device. locked blocks are write-protected from program and erase operations. to lock all of the blocks in the device, issue the lock (2ah) command. when a program or erase operation is issued to a locked block, r/b# goes low for t lbsy. the program or erase operation does not complete. any read status com- mand reports bit 7 as 0, indicating that the block is protected. the lock (2ah) command is disabled if lock is low at power-on or if the device is locked tight. figure 49: lock operation lock command cle ce# we# i/ox 2ah micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
lock tight (2ch) the lock tight (2ch) command prevents locked blocks from being unlocked and al- so prevents unlocked blocks from being locked. when this command is issued, the unlock (23h) and lock (2ah) commands are disabled. this provides an additional level of protection against inadvertent program and erase operations to locked blocks. to implement lock tight tight in all of the locked blocks in the device, verify that wp# is high and then issue the lock tight (2ch) command. when a program or erase operation is issued to a locked block that has also been locked tight, r/b# goes low for t lbsy. the program or erase operation does not complete. the read status (70h) command reports bit 7 as 0, indicating that the block is protected. program and erase operations complete successfully to blocks that were not locked at the time the lock tight command was issued. after the lock tight command is issued, the command cannot be disabled via a soft- ware command. the only ways to disable the lock tight status is to power cycle the device. when the lock tight status is disabled, all of the blocks become locked, the same as if the lock (2ah) command had been issued. the lock tight (2ch) command is disabled if lock is low at power-on. figure 50: lock tight operation lock-tight command lock wp# cle ce# we# i/ox r/b# dont care 2ch micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 51: program/erase issued to locked block r/b# i/ox program or erase address/data input confirm 70h 60h t lbsy locked block read status block lock read status (7ah) the block lock read status (7ah) command is used to determine the protection status of individual blocks. the address cycles have the same format, as shown below, and the invert area bit should be set low. on the falling edge of re# the i/o pins out- put the block lock status register, which contains the information on the protection status of the block. table 16: block lock status register bit definitions block lock status register definitions i/o[7:3] i/o2 (lock#) i/o1 (lt#) i/o0 (lt) block is locked tight x 0 0 1 block is locked x 0 1 0 block is unlocked, and device is locked tight x 1 0 1 block is unlocked, and device is not locked tight x 1 1 0 figure 52: block lock read status block lock read status block address cle ce# we# ale re# i/ox 7ah add 1 add 2 add 3 status t whr micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 53: block lock flowchart power-up power-up with lock high lock tight cmd with wp# and lock high lock-tight cmd with wp# and lock high lock-tight cmd with wp# and lock high unlock cmd with invert area bit = 1 wp# low >100ns or lock cmd wp# low >100ns or lock cmd unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 0 entire nand flash array locked entire nand flash array locked tight block lock function disabled unlocked range locked range unlocked range unlocked range locked tight range unlocked range locked tight range unlocked range locked-tight range power-up with lock low (default) locked range unlocked range locked range micron confidential and proprietary 1gb: x8, x16 nand flash memory block lock feature pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
one-time programmable operations (3.3v) this micron nand flash device offers a protected, one-time programmable (otp) nand flash memory area. ten full pages (2112 bytes or 1056 words per page) of otp data is available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. the otp area can be used in a num- ber of ways; typical uses include programming serial numbers or other data for perma- nent storage. in micron nand flash devices, the otp area leaves the factory in an unwritten state (each otp bit is 1). programming or partial-page programming enables the user to pro- gram the otp area with only 0s. the otp area cannot be erased, whether it is protected or not. protecting the otp area prevents further programming of that area. micron provides a unique way to program and verify data before permanently protect- ing it and preventing future changes. otp programming and protection are accomplish- ed in two discrete operations. first, the otp data program (a0h-10h) command is used to program an entire otp page in one operation or to perform up to four partial- page programming sequences. programming can occur on other pages within the otp area in a similar manner. second, the otp area is permanently protected from further programming using the otp data protect (a5h-10h) command. pages within the otp area can be read using the otp data read (afh-30h) command, whether it is protected or not. otp data program (a0h-10h) the otp data program (a0h-10h) command is used to write data to the pages with- in the otp area. an entire page can be programmed at one time, or a page can be partially programmed up to eight times. there is no erase operation for the otp pages. the otp data program enables programming into an offset of an otp page, using the two bytes of column address (ca[11:0]). the otp data program command will not execute if the otp area has been protected. if the otp area is protected, the busy time for the otp data program operation is t obsy (not t prog). to use the otp data program command, issue the a0h command. issue four ad- dress cycles: for the first two address cycles, select the column address; for the other two cycles, select a page in the 02hC0bh range. next, write the data using 1C2112 bytes of data (x8 device). after data input is complete, issue the 10h command. the internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. program verification only de- tects 1s that are not successfully written to 0s. random data input (85h) commands are supported during otp data program operations only if the otp area is unprotected. r/b# goes low during the duration of the array programming time ( t prog). the read status (70h) command is the only command valid during the otp data program operation. for this operation, bits 5 and 6 of the status register reflect the state of r/b#. if bit 7 is 0, then the otp area has been protected; otherwise, it is 1. when the device is ready, read bit 0 of the status register to determine whether the oper- ation passed or failed (see status register definition). micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (3.3v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 54: otp data program operation we# ce# ale cle re# r/b# i/ox dont care otp data written (following good status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2112 bytes a0h col add 1 col add 2 d in n d in m 00h 10h 70h status otp page 1 otp address 1 note: 1. the otp page must be within the 02hC0bh range. otp data protect (a5h-10h) the otp data protect (a5h-10h) command is used to protect all the data in the otp area. when the otp area is protected, the pages within the area are no longer program- mable and cannot be unprotected. to use the otp data protect command, issue the a5h command; then issue the fol- lowing four address cycles: 00h-00h-01h-00h, followed by the 10h command. r/b# goes low while the otp area is being protected. the protect command duration is similar to a normal page programming operation, t prog. the read status (70h) command is the only command valid during the otp data protect operation. for this operation, bits 5 and 6 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine whether the oper- ation passed or failed (see status register definition). micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (3.3v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 55: otp data protect operation we# ce# ale cle re# r/b# i/ox dont care t wc t wb t prog otp data protect command otp address otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h note: 1. otp data is protected following a good status confirmation. otp data read (afh-30h) the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether the area is protected or not. to use the otp data read command, issue the afh command; then issue four ad- dress cycles: for the first two cycles, select the column address; for the other two cycles, select a page in the range of 02hC0bh. then issue the 30h command. random data read (05h-e0h) commands are supported during otp data read operations. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. for this operation, bits 5 and 6 of the sta- tus register reflect the state of r/b#. for details, refer to see status register definition. normal read operation timings apply to otp read accesses (see the figure below). ad- ditional pages within the otp area can be selected by repeating the otp data read command. note that if otp data read is followed by page read cache mode, a reset (ffh) must be issued prior to issuing the page read cache mode command. the maxi- mum reset time will not exceed 5 s. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (3.3v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 56: otp data read operation we# ce# ale cle re# r/b# i/ox busy t r afh 00h 30h col add 1 col add 2 dont care otp page 1 otp address d out n d out n + 1 d out m note: 1. the otp page must be within the 02hC0bh range. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (3.3v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
one-time programmable operations (1.8v) this micron nand flash device offers a protected, one-time programmable (otp) nand flash memory area. thirty full pages (2112 bytes per page) of otp data is availa- ble on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. the otp area can be used in a number of ways; typical uses include programming serial numbers or other data for permanent storage. in micron nand flash devices, the otp area leaves the factory in an unwritten state (all bits are 1s). programming or partial-page programming enables the user to program the otp area with only 0s. the otp area cannot be erased, whether it is protected or not. protecting the otp area prevents further programming of that area. micron provides a unique way to program and verify data before permanently protect- ing it and preventing future changes. the otp area is only accessible while in otp operation mode. to set the device to otp operation mode, issue the set feature (efh) command to feature address 90h and write 01h to p1, followed by three cycles of 00h to p2Cp4. when the device is in otp operation mode, all subsequent page read (00h-30h) and program page (80h-10h) commands are applied to the otp area. the otp area is assigned to page addresses 02hC1eh. to program an otp page, issue the program page (80h-10h) command. the pages must be programmed in ascending order. to read an otp page, issue the page read (00h-30h) command. the otp area can be protected page by page using the otp protect mode. to set the device to otp protect mode, issue the set feature (efh) command to feature ad- dress 90h and write 03h to p1, followed by three cycles of 00h to p2Cp4. to protect a page in the otp area, issue the 80h command, followed by four address cycles (00h-00h-page address-00h), followed by one data cycle of 00h, followed by the 10h command. r/b# goes low for t prog. to determine whether the device is busy during an otp operation, monitor r/b# or use the read status (70h) command. to exit otp operation or protect mode, write 00h to p1 at feature address 90h. otp data program (80h-10h) the otp data program (80h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or a page can be partially programmed up to eight times. only the otp area allows up to eight partial-page pro- grams. the rest of the blocks support four partial-page programs. there is no erase operation for otp pages. program page enables programming into an offset of an otp page, using the two bytes of column address (ca[12:0]). the command is compatible with the random da- ta input (85h) command. the program page command will not execute if the otp area has been protected. to use the program page command, issue the 80h command. issue four address cy- cles: for the first two address cycles, select the column address; for the other two cycles, select a page in the range of 02h-00h through 1eh-00h. next, write 1C2112 bytes of data. after data input is complete, issue the 10h command. the internal control logic auto- micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
matically executes the proper programming algorithm and controls the necessary tim- ing for programming and verification. r/b# goes low for the duration of the array programming time ( t prog). the read status (70h) command is the only valid command for reading status in otp operation mode. bit 5 of the status register reflects the state of r/b#. when the device is ready, read bit 0 of the status register to determine whether the operation passed or failed. each otp page can only be programmed one time. if a program page command is issued to the otp area after the area has been protec- ted, r/b# will go low for t obsy. random data input (85h) after the initial otp data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input command can be used any number of times in the same page prior to the otp page write (10h) command being issued. figure 57: otp data program operation (after entering otp operation mode) we# ce# ale cle re# r/b# i/ox dont care otp data written (following good status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2112 bytes x16 device: m = 1056 words 80h col add 1 col add 2 d in n d in m 00h 10h 70h status otp page 1 otp address 1 note: 1. the otp page must be within the 02hC1eh range. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 58: otp data program with random data input (after entering otp operation mode) we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add1 col add2 otp page 1 d in n+1 t adl t adl random data input command column address program command read status command serial input 85h col add1 70h status 10h t prog t wb dont care 00h d in n col add2 d in n d in n+1 note: 1. the otp page must be within the 02hC1eh range. otp data protect (80h-10h) the otp area is protected on a page basis. to protect a page or all pages, set the device to otp protect mode, then issue the program page (80h-10h) command and write page address to protect a specific page. to set the device to otp protect mode, issue the set feature (efh) command to feature address 90h and write 03h to p1, followed by three cycles of 00h to p2Cp4. after the data is protected, it cannot be programmed further. when the otp area is pro- tected, the pages within the area are no longer programmable and cannot be unprotected. to use the program page command to protect the otp area, issue the 80h com- mand; then issue the following four address cycles: 00h-00h-page address-00h and write 00h data, followed by the 10h command. if an otp data program command is issued after the otp area has been protected, r/ b# will go low for t obsy. the read status (70h) command is the only valid command for reading status in otp operation mode. bit 5 of the status register reflects the state of r/b#. when the device is ready, read bit 0 of the status register to determine whether the oper- ation passed or failed. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 59: otp data protect operation (after entering otp protect mode) we# ce# ale cle re# r/b# i/ox dont care t wc t wb t prog otp data protect command otp address otp data protected 1 program command read status command 80h col 00h col 00h 10h 70h status otp page 00h note: 1. otp data is protected following a good status confirmation. otp data read (00h-30h) to read data from the otp area, set the device to otp operation mode, then issue the page read (00h-30h) command. data can be read from otp pages within the otp area whether the area is protected or not. to use the page read command for reading data from the otp area, issue the 00h command; then issue four address cycles: for the first two cycles, select the column ad- dress; for the other two cycles, select a page in the range of 02h-00h-00h through 1eh-00h-00h. then issue the 30h command. the page read cache mode command is not supported on otp pages. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command is the only valid command for reading status in otp operation mode. bit 5 of the status register reflects the state of r/b#. normal read operation timings apply to otp read accesses. additional pages within the otp area can be selected by repeating the otp data read command. the page read command is compatible with the random data output (05h-e0h) command. only data on the current page can be read. pulsing the re# pin outputs data sequentially. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 60: otp data read operation we# ce# ale cle re# r/b# i/ox busy t r 00h 00h 30h col add 1 col add 2 dont care otp page 1 otp address d out n d out n + 1 d out m note: 1. the otp page must be within the 02hC1eh range. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 61: otp data read with random data read operation we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 otp page 1 00h 00h t r t ar t rr dont care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t whr t clr d out n d out n + 1 30h t wb column address n column address m note: 1. the otp page must be within the range 02hC1eh. micron confidential and proprietary 1gb: x8, x16 nand flash memory one-time programmable operations (1.8v) pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
write protect operation the program and erase commands can be enabled and disabled using the wp# pin. the following six figures illustrate the setup time ( t ww) required from wp# toggling un- til a program or erase command is latched into the command register. after com- mand cycle 1 is latched, the wp# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is 1). figure 62: erase enable t ww 60h d0h we# i/ox wp# r/b# figure 63: erase disable t ww 60h d0h we# i/ox wp# r/b# micron confidential and proprietary 1gb: x8, x16 nand flash memory write protect operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 64: program enable t ww 80h 10h (or 15h) we# i/ox wp# r/b# figure 65: program disable t ww 80h 10h (or 15h) we# i/ox wp# r/b# micron confidential and proprietary 1gb: x8, x16 nand flash memory write protect operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 66: program for internal data move enable t ww 85h 10h we# i/ox wp# r/b# figure 67: program for internal data move disable t ww 85h 10h we# i/ox wp# r/b# micron confidential and proprietary 1gb: x8, x16 nand flash memory write protect operation pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
error management each nand flash die (lun) is specified to have a minimum number of valid blocks (nvb) of the total available blocks. this means the die (luns) could have blocks that are invalid when shipped from the factory. an invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ecc. additional blocks can develop with use. however, the total number of available blocks per die (lun) will not fall below nvb during the endurance life of the product. although nand flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error-correction algo- rithms. this type of software environment ensures data integrity. internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to program the bad-block mark into every loca- tion in the first page of each invalid block. it may not be possible to program every location with the bad-block mark. however, the first spare area location in each bad block is guaranteed to contain the bad-block mark. this method is compliant with on- fi factory defect mapping requirements. see the following table for the first spare area location and the bad-block mark. system software should check the first spare area location on the first page of each block prior to performing any program or erase operations on the nand flash de- vice. a bad block table can then be created, enabling system software to map around these areas. factory testing is performed under worst-case conditions. because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? always check status after a program or erase operation ? under typical conditions, use the minimum required ecc (see table below) ? use bad-block management and wear-leveling algorithms the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. blocks 0-7 (block address 00h-40h) guaranteed to be valid with ecc when shipped from factory (3.3v only). blocks 0-3 (block address 00h-40h) guaranteed to be valid with ecc when shipped from factory (1.8v only). table 17: error management details description requirement minimum number of valid blocks (nvb) per lun 1004 total available blocks per lun 1024 first spare area location x8: byte 2048 x16: word 1024 bad-block mark x8: 00h x16: 0000h minimum required ecc 1-bit ecc per 528 bytes of data micron confidential and proprietary 1gb: x8, x16 nand flash memory error management pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications stresses greater than those listed can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods can affect reliability. table 18: absolute maximum ratings voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input 3.3v v in C0.6 +4.6 v 1.8v C0.6 +2.4 v v cc supply voltage 3.3v v cc C0.6 +4.6 v 1.8v C0.6 +2.4 v storage temperature t stg C65 +150 c short circuit output current, i/os C C 5 ma table 19: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0 C +70 c industrial C40 C +85 c v cc supply voltage 3.3v v cc 2.7 3.3 3.6 v 1.8v 1.65 1.8 1.95 v ground supply voltage v ss 0 0 0 v table 20: valid blocks parameter symbol device min max unit notes valid block number nvb 3.3v/1.8v 1004 1024 blocks 1, 2 notes: 1. invalid blocks are blocks that contain one or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below nvb during the endurance life of the device. do not erase or program blocks marked invalid by the factory. 2. blocks 0C7 (3.3v) and blocks 0C3 (1.8v) are guaranteed to be valid with ecc when ship- ped from the factory. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 21: capacitance description symbol max unit notes input capacitance c in 10 pf 1, 2 input/output capacitance (i/o) c io 10 pf 1, 2 notes: 1. these parameters are verified in device characterization and are not 100% tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. table 22: test conditions parameter value notes input pulse levels 0.0v to v cc input rise and fall times 5ns input and output timing levels v cc /2 output load 3.3v 1 ttl gate and cl = 30pf 1 1.8v 1 ttl gate and cl = 30pf 1 note: 1. these parameters are verified in device characterization and are not 100% tested. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications C ac characteristics and operating conditions table 23: ac characteristics: command, data, and address input (3.3v) parameter symbol min max unit notes ale to data start t adl 70 C ns 1 ale hold time t alh 5 C ns ale to setup time t als 10 C ns ce# hold time t ch 5 C ns cle hold time t clh 5 C ns cle setup time t cls 10 C ns ce# setup time t cs 15 C ns data hold time t dh 5 C ns data setup time t ds 10 C ns write cycle time t wc 25 C ns we# pulse width high t wh 10 C ns we# pulse width t wp 12 C ns wp# setup time t ww 100 C ns note: 1. timing for t adl begins in the address cycle on the final rising edge of we# and ends with the first rising edge of we# for data input. table 24: ac characteristics: command, data, and address input (1.8v) parameter symbol min max unit notes ale to data start t adl 100 C ns 1 ale hold time t alh 10 C ns ale setup time t als 15 C ns ce# hold time t ch 10 C ns cle hold time t clh 5 C ns cle setup time t cls 15 C ns ce# setup time t cs 25 C ns data hold time t dh 5 C ns data setup time t ds 15 C ns write cycle time t wc 35 C ns we# pulse width high t wh 15 C ns we# pulse width t wp 17 C ns wp# setup time t ww 100 C ns note: 1. timing for t adl begins in the address cycle on the final rising edge of we# and ends with the first rising edge of we# for data input. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 25: ac characteristics: normal operation (3.3v) note 1 applies to all parameter symbol min max unit notes ale to re# delay t ar 10 C ns ce# access time t cea C 25 ns ce# high to output high-z t chz C 30 ns 2 cle to re# delay t clr 10 C ns ce# high to output hold t coh 15 C ns output high-z to re# low t ir 0 C ns read cycle time t rc 25 C ns re# access time t rea C 20 ns re# high hold time t reh 10 C ns re# high to output hold t rhoh 15 C ns re# high to we# low t rhw 100 C ns re# high to output high-z t rhz C 100 ns 2 re# low to output hold t rloh 5 C ns re# pulse width t rp 12 C ns ready to re# low t rr 20 C ns reset time (read/program/erase) t rst C 5/10/500 s 3 we# high to busy t wb C 100 ns 4 we# high to re# low t whr 60 C ns notes: 1. ac characteristics may need to be relaxed if i/o drive strength is not set to full. 2. transition is measured 200mv from steady-state voltage with load. this parameter is sampled and not 100% tested. 3. the first time the reset (ffh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. thereafter, the device will be busy for maximum 5s. 4. do not issue a new command during t wb, even if r/b# is ready. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 26: ac characteristics: normal operation (1.8v) note 1 applies to all parameter symbol min max unit notes ale to re# delay t ar 10 C ns ce# access time t cea C 30 ns ce# high to output high-z t chz C 45 ns 2 cle to re# delay t clr 10 C ns ce# high to output hold t coh 15 C ns output high-z to re# low t ir 0 C ns read cycle time t rc 35 C ns re# access time t rea C 25 ns re# high hold time t reh 15 C ns re# high to output hold t rhoh 15 C ns re# high to we# low t rhw 100 C ns re# high to output high-z t rhz C 100 ns 2 re# pulse width t rp 17 C ns ready to re# low t rr 20 C ns reset time (read/program/erase) t rst C 5/10/500 s 3 we# high to busy t wb C 100 ns 4 we# high to re# low t whr 80 C ns notes: 1. ac characteristics may need to be relaxed if i/o drive strength is not set to full. 2. transition is measured 200mv from steady-state voltage with load. this parameter is sampled and not 100% tested. 3. the first time the reset (ffh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. thereafter, the device will be busy for maximum 5s. 4. do not issue a new command during t wb, even if r/b# is ready. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C ac characteristics and operating conditions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications C dc characteristics and operating conditions table 27: dc characteristics and operating conditions (3.3v) parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc1_a C 25 35 ma program current C i cc2_a C 25 35 ma erase current C i cc3_a C 25 35 ma i/o burst read current C i cc4r_a C 25 35 ma i/o burst write current C i cc4w_a C 25 35 ma bus idle current C i cc5_a C 2 3 ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb1 C C 1 ma standby current (cmos) ce# = v cc - 0.2v; wp# = 0v/v cc i sb_a C 10 50 a staggered power-up cur- rent rise time = 1ms line capacitance = 0.1f i st C C 10 ma 1 input leakage current v in = 0v to v cc i li C C 10 a output leakage current v out = 0v to v cc i li C C 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp# v ih 0.8 x v cc C v cc + 0.3 v input low voltage, all in- puts C v il C0.3 C 0.2 x v cc v output high voltage i oh = C400a v oh 0.67 x v cc C C v 2 output low voltage i ol = 2.1ma v ol C C 0.4 v 2 output low current v ol = 0.4v i ol (r/b#) 8 10 C ma 3 notes: 1. measurement is taken with 1ms averaging intervals and begins after v cc reaches v cc,min . 2. v oh and v ol may need to be relaxed if i/o drive strength is not set to full. 3. i ol (r/b#) may need to be relaxed if r/b# pull-down strength is not set to full. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C dc characteristics and operating conditions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 28: dc characteristics and operating conditions (1.8v) parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc1_a C 10 20 ma program current C i cc2_a C 10 20 ma erase current C i cc3_a C 10 20 ma i/o burst read current C i cc4r_a C 10 20 ma i/o burst write current C i cc4w_a C 10 20 ma bus idle current C i cc5_a C 2 3 ma stanbdy current (ttl) ce# = v ih ; lock = wp# = 0v/v cc i sb1 C C 1 ma standby current (cmos) ce# = v cc - 0.2v; lock = wp# = 0v/v cc i sb_a C 10 50 a staggered power-up cur- rent rise time = 1ms line capacitance = 0.1f i st C C 10 ma 1 input leakage current v in = 0v to v cc i li C C 10 a output leakage current v out = 0v to v cc i lo C C 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp#, lock v ih 0.8 x v cc C v cc + 0.3 v input low voltage, all in- puts C v il C0.3 C 0.2 x v cc v output high voltage i oh = C100a v oh v cc - 0.1 C C v 2 output low voltage i ol = +100a v ol C C 0.1 v 2 output low current v ol = 0.4v i ol (r/b#) 3 4 C ma 3 notes: 1. measurement is taken with 1ms averaging intervals and begins after v cc reaches v cc,min . 2. v oh and v ol may need to be relaxed if i/o drive strength is not set to full. 3. i ol (r/b#) may need to be relaxed if r/b# pull-down strength is not set to full. micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C dc characteristics and operating conditions pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications C program/erase characteristics table 29: program/erase characteristics parameter symbol typ max unit notes number of partial page programs nop C 4 cycles 1 block erase operation time t bers 0.5 2 ms busy time for program cache operation (3.3v) t cbsy 3 700 s 2 busy time for program cache operation (1.8v) t cbsy 3 700 s 2 busy time for set features and get features operations (3.3v) t feat C 1 s busy time for set features and get features operations (1.8v) t feat C 1 s busy time for program/erase on locked block t lbsy C 3 s last page program operation time t lprog C C C 3 busy time for otp data program operation if otp is protec- ted t obsy C 30 s page program operation time (1.8v) t prog 250 700 s page program operation time (3.3v) t prog 250 700 s data transfer from flash array to data register t r C 25 s busy time for read cache operation t rcbsy 3 25 s notes: 1. four total partial page programs to the same page. 2. t cbsy max time depends on timing between internal program completion and data-in. 3. t lprog = t prog (last page) + t prog (last - 1 page) - command load time (last page) - address load time (last page) - data load time (last page). micron confidential and proprietary 1gb: x8, x16 nand flash memory electrical specifications C program/erase characteristics pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
asynchronous interface timing diagrams figure 68: reset operation cle ce# we# r/b# i/o[7:0] t rst t wb ffh reset command figure 69: read status cycle re# ce# we# cle i/o[7:0] t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output dont care t cea t coh micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 70: read parameter page we# ale cle re# r/b# ech 00h t r p0 0 p1 0 p255 0 p0 1 t wb t rr i/o[7:0] t rp t rc figure 71: read page d out n d out n + 1 d out m we# ce# ale cle re# rdy i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz dont care col add 1 col add 2 row add 1 row add 2 micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 72: read page operation with ce# dont care re# ce# t rea t chz t coh t cea re# ce# ale cle i/ox i/ox out rdy we# data output t r dont care address (4 cycles) 00h 30h micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 73: random data read we# ce# ale cle re# rdy i/ox t rhw t rc dout m dout m + 1 col add 1 col add 2 05h e0h t rea t clr dout n C 1 dout n t whr column address m micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 74: read page cache sequential t wc we# ce# ale cle re# rdy i/ox column address 0 page address m column address 00h t cea t ds t clh t cls t cs t ch t dh t rr t wb t r t rc t rea 30h d out 0 31h col add 2 row add 1 row add 2 00h t rcbsy page address m col add 1 t rhw d out 1 t clh t ch t ds t wb t cls t cs d out 31h 1 we# ce# ale cle re# rdy i/ox column address 0 page address m t rc t rea d out 0 t rhw d out 1 dont care column address 0 t clh t ch t rea t cea t rhw t ds t rr t rcbsy t wb column address 0 d out 0 d out 3fh d out 0 d out t cls t cs t rc d out 31h t rcbsy d out 1 d out 1 page address m + 1 page address m + 2 1 t dh t dh micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 75: read page cache random t wc we# ce# ale cle re# rdy i/ox column address 00h t ds t clh t cls t cs t ch t dh t wb t r 30h 00h col add 2 row add 1 row add 2 00h page address m col add 1 column address 00h col add 2 row add 1 row add 2 page address n col add 1 1 we# ce# ale cle re# rdy i/ox dont care column address 0 t ch t rea t cea t rhw t ds t dh t rr t rcbsy t wb column address 0 d out 0 d out 3fh d out 0 d out t cs t rc 31h t rcbsy d out 1 d out 1 page address m page address n column address 00h col add 2 row add 1 row add 2 page address n col add 1 1 t clh t cls micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 76: read id operation we# ce# ale cle re# i/ox address, 1 cycle 90h 00h or 20h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr figure 77: program page operation we# ce# ale cle re# rdy i/ox t wc t adl 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 d in n d in m 70h status 10h t prog t whr t wb dont care micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 78: program page operation with ce# dont care address (4 cycles) data input 10h we# ce# t wp t ch t cs dont care data input 80h cle ce# we# ale i/ox figure 79: program page operation with random data input we# ce# ale cle re# rdy i/ox t wc serial input 80h col add 1 col add 2 row add 1 row add 2 d in m d in n t adl t adl change write column command column address read status command serial input 85h t prog t wb t whr dont care col add 1 col add 2 d in p d in q 70h status 10h micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 80: program page cache we# ce# ale cle re# rdy i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 d in n d in m d in m d in n last page - 1 last page serial input t wc dont care 80h t adl figure 81: program page cache ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 d in n d in m d in n d in m last page last page C 1 serial input t wc dont care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page C 1 program successful t adl t whr t whr t adl micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 82: internal data move we# ce# ale cle re# rdy i/ox t wb t prog t wb busy busy read status command t wc dont care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n col add 1 00h col add 2 row add 1 row add 2 35h (or 30h) col add 1 85h data 1 t r data input optional figure 83: erase block operation we# ce# ale cle re# rdy i/o[7:0] read status command busy row address 60h row add 1 row add 2 70h status d0h t wc t bers t wb t whr dont care i/o0 = 0, pass i/o0 = 1, fail micron confidential and proprietary 1gb: x8, x16 nand flash memory asynchronous interface timing diagrams pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
revision history rev d, production C 01/10 ? new format release rev c, production C 7/09 ? x8 operational example table: corrected maximum addresses for block 0/page 1 and block 0/page 2 rev b, production C 5/08 ? updated part numbers and added part number and content to support the h4 device ? removed v cc power cycling section and added device initialization section rev a, production C 2/08 ? initial release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. micron confidential and proprietary 1gb: x8, x16 nand flash memory revision history pdf:09005aef83c2e425 1gb_nand_m58a.pdf C rev. d 1/10 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/

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